The present invention relates, in general, to bias control of the well region of a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) device, and more particularly, bias control of an N-well region of a PMOS device.
Complimentary MOS (CMOS) processing is used for semiconductors which employ both N-type and P-type devices. The N-type and P-type devices coexist on the same substrate through the use of well regions. The well regions act as isolation boundaries between the N-type and P-type devices and are typically electrically shorted to either the source or drain regions. CMOS devices are used, for example, for up/down, DC-DC voltage regulator controller applications. Both N-type and P-type MOS Field Effect Transistors, NMOS and PMOS, respectively, are used to control current flow from the voltage source, typically a battery. The NMOS device, for example, is typically used to conduct current from the voltage supply or battery to charge the inductor during up-conversion mode. The PMOS device, for example, is then used to conduct current from the inductor during the discharge cycle of the inductor. The PMOS device experiences a higher potential on the drain terminal as compared to the source terminal, for example, during up-conversion mode of the regulator. Down-conversion mode, however, renders the source terminal of the PMOS device at a higher potential than the drain terminal.
Prior art up/down, DC-DC converters which employ the PMOS and NMOS switch topology, typically employ the PMOS device with a fixed electrical connection to either the source or drain regions. Applying a fixed electrical connection to either the source or drain regions, however, can lead to problems such as latch up or leakage. In order to minimize latch up or leakage conditions, the well region of the PMOS and NMOS devices should be electrically shorted to the appropriate source or drain regions as necessary. In the case of a PMOS device, for example, the N-well region should be coupled to the source or drain region which is at the higher potential to minimize latch up probability. Conversely, NMOS devices should have the P-well region coupled to the source or drain region experiencing the lower potential, in order to minimize latch up probability. A need exists, therefore, for a bias control switch, capable of determining the correct bias to apply to the well region in order to minimize the occurrence of latch up.